基于极化码DJSCC的Fast-SSC译码及FPGA实现

Fast-SSC Decoding and FPGA Implement for Distributed Joint Source-Channel Coding Using Polar Code

针对基于极化码的分布式联合信源信道编码(Distributed Joint Source-Channel Coding,DJSCC)译码端复杂度高、吞吐率低的问题,提出了一种适用于基于极化码的DJSCC框架的快速简化串行抵消(Fast Simplified Successive Cancellation,Fast-SSC)译码方案,最后设计了对应的现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)实现方案。根据极化码冻结位与信息位的分布,将其码字划分成4种子码,译码方式可从逐个比特译码转为对每个子码并行译码,从而减少在树形SC译码器上的迭代层数。仿真结果表明,相较于在同等硬件框架下的串行抵消(Successive Cancellation,SC)译码算法,该算法可在几乎不损失误码率(Bit Error Rate,BER)性能的前提下,有效减少译码的迭代次数,从而提升译码的吞吐率。

To address the issues of high complexity and low throughput of DJSCC(Distributed Joint Source-Channel Coding)using polar codes at decoding side,a Fast-SSC(Fast Simplified Successive Cancellation)decoding scheme adapted to DJSCC framework using polar codes is proposed,and the corresponding FPGA(Field Programmable Gate Array)implementation is designed.Based on the distribution of frozen bits and information bits in polar codes,the code word is divided into four sub-codes,and the decoding scheme could be decoding the sub-codes in parallel rather than decoding bit by bit,which reduces the iteration on the decoding tree based on SC(Successive Cancellation).Simulation results indicate that compared with the SC decoding in the same hardware framework,the proposed algorithm can effectively reduce the iteration for decoder and enhances the throughput without tangibly altering the bit-error-rate performance.