基于TAS-TIS结构和前馈路径的两级CTLE的设计

Design of Two-Stage CTLE Equalizer Based on TAS-TIS Structure and Feed-Forward Path

在高速接口电路中,接收机通常采用连续时间线性均衡器(Continuous-Time Linear Equalizer,CTLE)消除符号间干扰(Inter-Symbol Interference,ISI)对信号传输的影响。为提高CTLE电路的高频增益和减少芯片面积,基于UMC(United Microelectronics Corporation)28 nm工艺,设计了一款最大速率为50 Gbps的CTLE电路,其主体电路由跨导级联跨阻抗(Trans-Admittance Trans-impedance,TAS-TIS)结构和前馈路径的两级CTLE电路构成。在传统CTLE的基础上,使用有源电感做负载,以反相器为基础构建跨阻放大器和在输入管增加前馈通路等方式,有效地扩展了电路的工作频率。仿真结果显示,均衡后40 Gbps PAM4(4-Level Pulse Amplitude Modulation)信号、50 Gbps PAM4信号和28 Gbps NRZ(Non Return Zero Code)信号的眼图眼宽分别达到了0.68,0.5,0.92个码元间隔(UI),可满足后级电路对于输入信号的要求,对提升整体传输数据速率具有重要的意义。

In high-speed interface circuits,receivers typically use Continuous-Time Linear Equalizer(CTLE)to eliminate the effects of Inter-Symbol Interference(ISI)on signal transmission.In order to improve the high-frequency gain of the CTLE circuit and reduce the chip area,a CTLE circuit with a maximum rate of 50 Gbps was designed based on the UMC(United Microelectronics Corporation)28 nm process.Its main circuit was composed of a two-stage CTLE circuit with a trans-admittance transimpedance(TAS-TIS)structure and feed-forward path.On the basis of traditional CTLE,the active inductor was used as the load,the transimpedance amplifier was built based on the inverter,and the feed-forward path was added to the input tube,which effectively expanded the operating frequency of the circuit.The simulation results show that the eye widths of the 40 Gbps PAM4(4-Level Pulse Amplitude Modulation)signal,50 Gbps PAM4 signal and 28 Gbps NRZ(Non Return Zero Code)signal reach 0.68,0.5,0.92 code element spacing(UI)respectively,which can meet the requirements of the post-stage circuit for input signals.It is of great significance to improve the overall transmission data rate.