基于FPGA的ZUC-256算法实现架构分析

Implementation and architecture analysis of ZUC-256 algorithm based on FPGA

分析了ZUC-256算法架构,针对算法中多输入模231-1加法,提出了多种适用于FPGA的实现架构。通过分析关键路径,提出全硬件和软硬协同等多种优化方案,可适用于不同的应用场景。以Zynq-7000系列FPGA为例,详细对比了各个方案的性能差异。经验证,提出的方案可同时适用于ZUC-128和ZUC-256算法,可以广泛应用于4G LTE和5G-NR移动通信中。

The ZUC-256 algorithm architecture is analyzed,and a couple of implementation architectures suitable for FPGA are proposed for the multiple-input modulo 231-1 adder.By analyzing the critical path,various optimization schemes such as full hard-ware and hardware-software codesign are proposed,which can be applied to different application scenarios.Taking Zynq-7000 FPGA for example,the performance differences of each scheme are compared in detail.It has been verified that the proposed scheme can be applied to both ZUC-128 and ZUC-256 algorithms,and can be widely used in 4G LTE and 5G-NR mobile commu-nication.