基于UltraScale架构FPGA的DDR3用户接口优化系统

DDR3 user interface solution based on UltraScale architecture FPGA

为满足高速传输系统领域对于实时、高速数据采集与缓存的需求,结合Xilinx提供的基于UltraScale架构的XCKU060,在了解FPGA与DDR3相应节点的定义与特性的基础上,对其引脚进行合理分配连接,使其能够成功在IP核上运行使用。为了方便用户在软件方面的使用,在此基础上对其控制器接口引入读写FIFO和读写逻辑控制模块,优化了接口封装,并在VIVADO软件对读写过程进行测试。该方法可满足高速、大容量、实时数据的读写要求,充分发挥了DDR3存储的灵活性。

In order to meet the needs of real-time and high-speed data acquisition cache in the field of high-speed transmission system combined with Xilinx′s XCKU060 based on Ultrascale architecture,on the basis of understanding the definitions and char-acteristics of the node corresponding to FPGA and DDR3,this design allocates all the pins that connect them properly,and make them run successfully on IP cores.For the convenience of users in the use of software,based on the above,read-write FIFO and read-write logic control modules are introduced to the controller interface,optimizing its interface encap sulation.The read-write process is tested in VIVADO software.The method can meet the high speed,large capacity,real-time data read-write require-ments,and take advantage of the flexibility of DDR3 storage.