资源密集型NTT算法硬件设计与实现研究

Research on Hardware Design and Implementation of Resource Intensive NTT Algorithm

目前BGV、BFV、CKKS等典型全同态密码算法中,多项式环上乘法运算资源占用大、性能慢,是全同态密码算法硬件高效实现的难点,通常采用快速数论变换(Number Theoretic Transforms,NTT)算法进行加速设计。通过分析资源密集型NTT算法硬件设计的关键问题,优化典型NTT算法流程,提出了多周期并行化与单蝶形单元流水化两种硬件设计方案,重点分析了流水化设计的核心要点,并给出模块整体结构及仿真验证结果,结合性能与资源消耗评估情况,为资源密集型NTT算法不同参数的实用化硬件设计提供参考。研究表明,在资源与性能折中的情况下,采用流水化设计具有较高的资源性能比,为优先选择方案。

At present,typical homomorphic cryptography algorithms such as BGV scheme,BFV scheme,CKKS scheme etc.have large resource consumption and slow performance in polynomial ring multiplication,which is the difficulty in efficient hardware implementation of homomorphic cryptography algorithms.The fast NTT(Number Theoretic Transforms)algorithm is usually used to accelerate the design.By analyzing the key issues in the hardware design of resource intensive NTT algorithms,as well as optimizing the typical NTT algorithm process,this paper proposes two kinds of hardware design schemes:multi-cycle parallelization and single butterfly unit pipelining.It focuses on analyzing the core points of pipelining design and gives the overall structure of the module and simulation verification results.Combined with performance and resource consumption evaluation,this provides a reference for practical hardware design of different parameters in resource intensive NTT algorithms.Research shows that in a trade-off between resources and performance,the use of pipelining design has a higher resource performance ratio and is the preferred choice.