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用于高密度三维集成的TSV设计

Design of TSV for High-Density 3D Integration
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摘要 三维集成技术的发展需要高密度和高深宽比的硅通孔(TSV)阵列。由于TSV填充材料与TSV衬底材料之间的热膨胀系数不匹配,TSV在使用或加工过程中会出现严重的热应力问题,造成器件失效甚至是晶圆损坏。设计了一种具有低热应力和高深宽比的中空TSV。单个TSV呈现橄榄球形状,TSV中部直径最大,其次是顶部的直径,最小的是底部直径。采用金属钨进行空心填充,因为钨的热膨胀系数与硅衬底的更匹配。当出现热失配时,空心填充使得空心结构为填充金属与硅的热膨胀提供了缓冲空间,能够大幅度减小TSV衬底所受到的热应力。仿真结果表明沿着TSV轴向方向和径向方向,热应力分别减小了62.4%和60.5%。基于设计的TSV结构,开发了一套基于8英寸(1英寸=2.54 cm)硅晶圆的工艺流程,成功实现了1600/mm^(2)超高密度阵列的加工制作,能够应用于高密度三维集成。 Development of 3D integration technology requires through-silicon via(TSV)arrays with high density and high aspect ratio.Due to the mismatch of thermal expansion coefficients between TSV filler materials and TSV substrate materials,there will be serious thermal stress problems during application or processing of TSVs,resulting in device failure and even wafer damage.A hollow TSV with low thermal stress and high aspect ratio was designed.Individual TSV exhibits a shape of a rugby ball with the largest diameter in the middle of the TSV,followed by the diameter at the top and the smallest at the bottom.Metallic tungsten was used for hollow filling because the coefficient of thermal expansion of tungsten was better matched with that of the silicon substrate.When the thermal mismatch occurs,the hollow filling enables the hollow structure to provide a buffer space for the thermal expansion of the filled metal and silicon,which can greatly reduce the thermal stress on the TSV substrate.The simulation results show that the thermal stresses decrease by 62.4%and 60.5%along the axial and radial directions of TSV,respectively.Based on the designed TSV structure,a set of 8-inch(1 inch=2.54 cm)Si wafer process flow was developed to successfully realize the fabrication of an ultra-high density array of 1600/mm^(2).It can be applied to high density 3D integration.
作者 乔靖评 贾士奇 刘瑞文 焦斌斌 陈静宇 孔延梅 叶雨欣 杜向斌 云世昌 余立航 Qiao Jingping;Jia Shiqi;Liu Ruiwen;Jiao Binbin;Chen Jingyu;Kong Yanmei;Ye Yuxin;Du Xiangbin;Yun Shichang;Yu Lihang(Microsystems Technology Laboratory,New Technology Development Department,Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;School of Integrated Circuits,University of Chinese Academy of Sciences,Beijing 100049,China;School of Advanced Technology,Xi'an Jiaotong-Liverpool University,Suzhou 215123,China)
出处 《微纳电子技术》 CAS 北大核心 2023年第11期1857-1862,共6页 Micronanoelectronic Technology
基金 国家重点研发计划(2021YFB2011700)。
关键词 硅通孔(TSV) 三维集成 热应力 高密度 高深宽比 through-silicon via(TSV) 3D integration thermal stress high-density high aspect ratio
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