一种抗噪声折叠宽范围低杂散小数分频锁相环

An anti-noise folding wide range low spur fractional-N PLL

由于电荷泵的电流失配,小数分频锁相环反馈路径上经整形的量化噪声会被折叠回低频偏处,恶化带内相位噪声的性能。文章提出一种自适应的抗噪声折叠技术,根据工作频率产生合适脉宽的电流以线性化环路,在全频带内避免噪声折叠的同时不恶化参考杂散性能;设计基于TSMC 130 nm CMOS工艺,锁相环覆盖的输出频率范围为0.6~2.7 GHz。仿真结果显示:当输出频率为2.0 GHz时,环路功耗为16 mW,积分抖动为1.98 ps,品质因数为-222 dB;在电荷泵中引入8%的失配后,提出的技术改善带内相位噪声达到7 dB。

With the current mismatch in charge pump,quantization noise on the feedback path of a fractional-N phase locked loop(PLL)might be folded back to low frequency offset,thus deteriorating the in-band phase noise performance.This paper proposed an adaptive anti-noise folding technique,which linearized the loop with pulsed current that has proper width according to the operating frequency.Noise folding could be avoided in overall output frequency range without decreasing the reference spur performance.The design was made with TSMC 130 nm CMOS technology,and the PLL covered an output frequency ranging from 0.6-2.7 GHz.The simulation results showed that the loop consumed 16 mW when generating an output frequency of 2.0 GHz,and the integrated jitter was 1.98 ps,corresponding to an FOM of-222 dB.With 8% mismatch in charge pump,the proposed technique improved the in-band phase noise by 7 dB.