SpaceWire多优先级分层调度交叉开关研究与设计

Research and design of SpaceWire multi-priority hierarchical scheduling crossbar

SpaceWire(SpW)路由是SpW网络的关键设备之一,采用纵横式交叉开关(crossbar switch)结构,由于SpW网络数据分组最大长度不固定,经典的滑动迭代轮询匹配(iSlip)调度算法并不适用。研究二维行波进位交换结构,提出一种多优先级分层调度的crossbar switch实现结构,为不同业务流量类型赋予不同优先级可以提高网络服务质量(QoS),采用基于仲裁反馈轮询(FBP)算法,在群组路由时具有良好输出公平性。通过向环型行波进位(CRCS)仲裁结构中插入寄存器分割组合逻辑组成流水结构降低组合延迟,提高最高系统频率,解决路由端口数量扩展的问题。使用可编程逻辑语言实现优先级数量和端口数量可配置的crossbar,CRCS结构具有资源占用少、仲裁速度快和易于扩展的特点。以4×4规模的crossbar switch为例,采用二维CRCS结构相比于线性扩展结构,仲裁逻辑单元数量节省67.3%,仲裁延迟降低约60%,在Xilinx V7系列现场可编程门阵列(FPGA)进行逻辑综合,行列各插入2级寄存器,即可满足最大规模下的SpW路由应用需求。

SpaceWire(SpW)router is one of the key devices in the SpW network.It adopts a crossbar switching structure.Since the maximum length of the data packet of the SpW network is not fixed,the classic interative round robin matching with slip(iSlip)algorithm is not applicable.This paper studies the two-dimensional ripple-carry switching structure and proposes a multi-priority hierarchical scheduling crossbar switch implementation structure.The network quality of service(QoS)can be enhanced by giving various traffic types varying priorities,and group routing output fairness can be achieved by employing an arbitration feedback-based polling algorithm(FBP).By inserting registers into the circular ripple-carry switching(CRCS)structure,the combinational logic is split and a pipelined structure is formed,lessening the combinational delay.Also,Inserting registers increases the maximum frequency of the system and makes it possible to expand the number of router ports.A crossbar with a configurable priority number and port number is implemented using programmable logic language.The CRCS structure has the advantages of resource-saving,fast arbitration,and high scalability.By using the two-dimensional CRCS structure instead of the linear expansion structure,a 4×4 crossbar switch as an example,the number of arbitration logic cells is decreased by 67.3%,and the arbitration delay is decreased by about 60%.When it is synthesized on the Xilinx V7 series field programable gate array(FPGA).A maximum of two register insertion layers each for rows and columns is sufficient for the SpW routers at the largest scale.