面向典型处理器架构的代码级侧信道仿真特性研究

On Simulation Characteristics of Code-Level Side Channel for Typical Processor Architecture

为解决传统侧信道分析依赖硬件采集设备、检测流程靠后等问题,研究代码级侧信道仿真分析技术,通过监测记录密码软件代码在处理器运行期间的内存地址、寄存器值等信息,模拟代码执行过程中可能发生的泄漏.本文在已有研究基础上,针对X86、ARM、SPARC、PowerPC、MIPS等主流处理器架构进行拓展,通过交叉编译和处理器虚拟化技术对AES-128开源实现进行了跨平台寄存器仿真功耗采集和侧信道分析,探究对比在不同处理器架构下代码级侧信道仿真的特性.实验发现X86(rax/rcx/rdx)、ARM(r1/r2/r3)、MIPS(v0/v1)、PowerPC(r8/r9/r10)、SPARC(g1/g2/g3)等寄存器上存在数据拷贝、异或操作引起的功耗泄漏,由于精简指令集/复杂指令集的区别呈现泄漏的差异性特征.最后,按照源代码函数功能对寄存器泄漏情况进行分类,从而验证代码级侧信道仿真在多种处理器架构上的适用性程度.

In order to solve the problems of traditional side-channel analysis relying on hardware acquisition equipment and late detection process,the code-level side-channel simulation analysis technology is studied.The code execution is simulated by monitoring and recording the memory address and register value of the cryptographic software code during the operation of the processor.Leaks may occur during the process of code execution.Based on the known research results,this paper expands the mainstream processor architectures such as X86,ARM,SPARC,PowerPC and MIPS,carries out cross-platform register simulation power acquisition and side channel analysis for the open source implementation of AES-128 using cross-compilation and processor virtualization technology explores and compares the characteristics of code-level side channel simulation under different processor architectures.Experiments show that,X86(rax/rcx/rdx),ARM(r1/r2/r3),MIPS(v0/v1),PowerPC(r8/r9/r10),SPARC(g1/g2/g3)registers have power leakage caused by data copy and XOR operation.Because of the difference between the simple instruction set and the complex instruction set,the difference feature of leakage is presented.Finally,the register leakage is classified according to the function of source code,so as to verify the applicability of code-level side channel simulation on a variety of processor architectures.