摘要
随着集成电路工艺的不断发展,因电路工作主频的提升和工艺偏差影响的加剧,导致多输入转换(MIS)效应对电路静态时序分析的影响愈发不容忽视,使得传统的单输入转换(SIS)模式单元时序建库方式难以规避保持时间和建立时间的违规。为了表征MIS效应在时序分析中的影响,近年来多个MIS延时模型被提出,但目前大多数模型忽略了输入转换时间和负载对MIS效应的影响,因此精度不高。同时这些模型分别对每个单元进行建模,忽略了MIS效应与单元的晶体管级拓扑结构的关系,进一步影响了表征精度且需要较高表征成本。本文提出了一种基于异质图神经网络的MIS单元延时预测框架,将多输入单元的晶体管级拓扑电路建模成为异质图,利用异质图对影响MIS延时因素进行了全面且有效的表征,多个输入门的MIS效应可以训练为统一模型。在16 nm工艺下,该模型在多组多输入单元上进行了验证。实验结果表明,该模型在将建模开销减少至ANN模型所需开销8.8%的情况下,对于单元的平均误差仅为1.19%,相比ANN模型,精度提高了2.05倍。
With the advancement of integrated circuit technology and the increasing operating frequency of circuits,the impact of MultipleInput Switching(MIS)effects on circuit static timing analysis has become more prominent,exacerbated by process variations.Traditional SingleInput Switching(SIS)timing library construction methods struggle to handle violations of hold time and setup time.In recent years,several MIS delay models have been proposed to characterize the influence of MIS effects in timing analysis.However,most of these models overlook the impact of input switching time and load on MIS effects,resulting in pessimistic and less accurate predictions.Furthermore,these models individually model each unit without considering the relationship between MIS effects and the transistorlevel topology of the unit,leading to decreased accuracy and higher characterization costs.To address these challenges,this paper proposes a novel MIS unit delay prediction framework based on heterogeneous graph neural networks.The transistorlevel circuitry of multipleinput units is modeled as a heterogeneous graph,providing a comprehensive and effective representation of factors influencing MIS delay.Multipleinput gate MIS effects are trained as a unified model within this framework.In the context of the 16 nm process,the proposed model is validated on multipleinput units.The experiment results indicate that while reducing the modeling cost to 8.8%of the cost required by the ANN model,the model achieves an average error of only 1.19%for units.Compared to the ANN model,the accuracy has improved 2.05 times.
作者
丁文杰
姜海洋
张展华
曹鹏
DING Wenjie;JIANG Haiyang;ZHANG Zhanhua;CAO Peng(National ASIC System Engineering Technology Research Center,Southeast University,Nanjing 210096,China)
出处
《集成电路与嵌入式系统》
2024年第1期32-38,共7页
INTEGRATED CIRCUITS AND EMBEDDED SYSTEMS
基金
国家自然科学基金(62174031)。
关键词
多输入转换
异质图神经网络
单元延时模型
静态时序分析
multiple input switching
heterogeneous graph neural networks
cell delay model
static timing analysis