基于归一化模板匹配算法的动作电位检测IC

Action potential detection IC based on normalized template matching algorithm

针对多通道神经元动作电位(AP)信号采集硬件系统中,前端采集IC因电极阻抗、应用环境、系统功耗以及系统面积等因素而导致原始信号信噪比较低的问题,设计一种基于归一化模板匹配算法的AP信号检测IC。该检测IC基于模板匹配算法,并引入信号归一化以去除冗余信息。为确保芯片的实时性并降低功耗,芯片整体采用三级流水线结构,各个模块间插入门控时钟,同时可通过SPI总线配置更新其工作状态。在SMIC 180 nm数字工艺下,裸片面积为0.98 mm^(2),配置模板信息时功耗为701μW,完全工作时功耗为8.07 mW,且采用QFN48封装形式。测试结果表明,所设计的AP信号检测IC具有较好的抗噪性能,可用于信噪比较低的环境来降低信号传输带宽,即使在-10 dB信噪比环境下,评价模型综合性能的F1-Score仍可达到94.65%。

In allusion to the problem of low signal‐to‐noise ratio of the original signal caused by factors such as electrode impedance,application environment,system power consumption,and system area in the front‐end acquisition IC of multi‐channel neuron action potential(AP)signal acquisition hardware system,a normalized template matching algorithm based AP signal detection IC is designed.Based on template matching algorithm,signal normalization is introduced to detection IC to remove redundant information This detection IC utilizes a template matching algorithm and introduces signal regularization to remove redundant information.To ensure real‐time performance and reduced power consumption,a three‐stage pipeline structure is adopted at the chip,clock gating is inserted between modules,and its operational status can be updated via an SPI bus.Fabricated under the SMIC 180 nm digital process,the die area of the IC is 0.98 mm^(2),with a power consumption of 701μW during template configuration and 8.07 mW when fully operational,and it is packaged in a QFN48 format.Testing results indicate that the IC demonstrates good noise resistance,even under a-10 dB signal‐to‐noise ratio environment,achieving an F1‐Score of 94.65%in evaluating the model composite performance.