一种低回踢噪声低失调高频CMOS比较器

A Low Kickback Noise Low Offset High Frequency CMOS Comparator

动态比较器在高速高精度模数转换器中至关重要,针对失调和回踢噪声等指标,提出了一种可有效抑制回踢噪声的低失调电压高频动态比较器。所提出的比较器在预放大器中增加一对交叉耦合的MOS电容,中和输出节点的寄生电容,从而抑制回踢噪声,稳定高频输入信号;将锁存器的单尾电流源改为差分双尾源结构,同时跨接一个钟控MOS开关,有效实现了失调电压的抑制以及复位和再生的加速。采用TSMC 40 nm/0.9 V标准CMOS工艺和Cadence Spectre工具,对比较器的输入、失调、延迟和功耗特性进行分析仿真。结果表明:在1 GHz高频采样时钟频率和输入差模电压50 mV的条件下,回踢噪声和失调电压分别减小到22.297 mV和11μV,两种非理想特性被显著抑制;整体比较器的延时时间仅为0.061 ns,功耗为23.3μW,在高速高频Flash ADC、并行ADC等应用方向具有明显优势。

A dynamic comparator is the key component in high-speed and high-precision analog-to-digital converters.Aiming at perform-ance indicators such as offset and kickback noise,a low-offset high-frequency dynamic comparator that can effectively suppress kickback noise is proposed.By adding cross-coupled MOS capacitor pairs in the pre-amplifier,the parasitic effects on the output node can be neu-tralized to suppress the kickback noise and stabilize the high-frequency input signal.As well,a differential double-tail source structure in latch is used to replace single-tail current,with a clock-controlled MOS switch added simultaneously,it effectively realizes the sup-pression of offset voltage and the acceleration of reset and regeneration operation.Based on TSMC 40 nm/0.9 V standard CMOS process and Cadence Spectre tools,the comparator performance in terms of offset voltage,delay time,and power consumption are analytically simulated.The results show that,with 1 GHz sampling frequency and differential-mode input voltage in 50 mV,the kickback noise and offset voltage are effectively reduced to 22.297 mV and 11μV respectively.The delay time is only 0.061 ns and the power consumption is 23.3μW,which has significant advantages to be applied in high-speed and high-frequency Flash ADC and parallel ADC.