摘要
为提升各种微处理器与嵌入式系统的通信波特率,文章对传统波特率自适应检测技术加以改进,基于FPGA和Verilog HDL硬件描述语言设计一种可灵活高效配置波特率参数的UART模块。首先改进传统的通过发送固定数据检测波特率的技术,利用特征值匹配法结合查表比对法设计自适应波特率发生器,实现自动高效检测波特率,完成相应参数配置。然后采用Modelsim对各模块功能进行系统级仿真。仿真结果表明,该波特率发生器能够自动建立串口通信链路,数据传输稳定可靠,提高了检测效率,减少了系统资源开销。
To improve the communication baud rate between various microprocessors and embedded systems,this paper improves the traditional baud rate adaptive detection technology and designs a UART module based on FPGA and Verilog HDL hardware description language that canflexibly and efficiently configure baud rate parameters.Firstly,the traditional technique of detecting baud rate by sendingfixed data is improved,and an adaptive baud rate generator is designed using feature value matching method combined with table lookup comparison method to achieve automatic and efficient detection of baud rate and complete corresponding parameter configuration.Then use Modelsim to perform system level simulations on the functions of each module.The simulation results show that the baud rate generator can automatically establish a serial communication link,ensure stable and reliable data transmission,improve detection efficiency,and reduce system resource overhead.
作者
肖文桂
XIAO Wengui(Beijing University of Technology,Beijing 100124,China)
出处
《现代信息科技》
2024年第1期59-62,共4页
Modern Information Technology