基于面向TTE的新型数据综合系统的设计与实现

Design and Implementation of New Data Synthesis System for TTE

针对传统总线无法实时网络传输,新型总线时间触发以太网(TTE)兼容IP协议和IEEE802.3协议,但TT业务和BE业务需设备满足TTE协议,实际工程缺少适用性的问题,设计了一种基于FPGA的时间触发以太网数据综合系统。该数据综合系统以FPGA作为核心控制器,千兆网作为主要通信接口,在满足高速率、高宽带、高灵活的前提下,设计出数据综合模块,将多种传统总线与TTE总线良好兼容。试验结果表明:系统在同步精度高达40 ns、通信抖动仅为392 ns的前提下,数据转换收发无误码现象。同时将多种数据混合编帧,具备极高的稳定性与灵活性,为TTE网络数据服务于实际工程提供了可靠的解决方案。

In response to the inability of traditional buses for real-time network transmission,the new bus time triggered Ethernet(TTE)is compatible with the IP protocol and IEEE802.3 protocol.However,the TT and BE services require equipment to meet the TTE protocol,which is a problem of lack of applicability in practical engineering..A time triggered Ethernet data synthesis system based on FPGA was designed.The data integration system used FPGA as the core controller and gigabit network as the main communication interface.Under the premise of meeting high-speed,high bandwidth,and high flexibility,a data integration module was designed,which is well compatible with various traditional buses and TTE buses.The experimental results show that the system has a synchronization accuracy of up to 40 ns and communication jitter of only 392 ns,and there is no error in data conversion and transmission.At the same time,multiple types of data are mixed for framing,which has extremely high stability and flexibility,providing a reliable solution for TTE network data service in practical engineering.