集成电路制造中的良率提升与签核方法分析

Analysis of Yield Improvement and Signoff Methods in Integrated Circuit Manufacturing

阐述签核(Signoff)与EDA之间的融合关系,探讨良率提升签核可以贯穿在晶圆厂制造过程中,为每阶段的工作提供可量化、可对标的技术工程指标,来表征芯片良率的重要性。通过系统性方法学、签核Signoff流程以及高维度宏观的良率管理,可有效地为集成电路的高质量、良率、性能和可靠性保驾护航。同时也表明Yield Enhancement Signoff工具可结合各种数据进行分析,通过设计测试芯片和优化测试流程,在集成电路生态系统中可不断地促进良率提升。

This paper describes the fusion relationship between Signoff and EDA,and explores the importance of improving chip yield by providing quantifiable and benchmarking technical engineering indicators for each stage of work throughout the wafer manufacturing process.Through systematic methodology,signoff process,and high-dimensional macro yield management,the high quality,yield,performance,and reliability of integrated circuits can be effectively safeguarded.It also indicates that the Yield Enhancement Signoff tool can combine various data for analysis,and by designing test chips and optimizing test processes,it can continuously promote yield improvement in the integrated circuit ecosystem.