期刊文献+

微系统封装关键工艺设备发展现状及国产化分析

Analysis of Development Status and Domestic Production Process for Electronics Manufacturing Equipment Used in Microsystem Packaging
下载PDF
导出
摘要 以硅通孔(TSV)、再布线(RDL)、微凸点(Bumping)、封装组装为典型特征的微系统封装技术已成为后摩尔时代集成电路发展的新趋势,其实现途径的主要基础工艺包括光刻、刻蚀、薄膜沉积、电镀、键合、减薄等。从微系统封装工艺出发,系统梳理了主要工艺设备需求、发展现状以及国产化进展。通过现状及趋势的分析对比,认为微系统封装技术已进入行业发展机遇期,其所需的工艺设备对制程节点要求相对较低,对设备种类要求较多,可作为制造设备国产化的重要平台大力发展,提升半导体产业链供应链韧性与安全水平。 Three-dimensional stacking process represented by Through Silicon Via(TSV),Re-Distributed Layer(RDL),micro bump,and advanced packaging,which integrates modules with different functions and materials onto a single chip,has become a new trend in the development of integrated circuits in the post-Moore era.The main basic processes for its implementation include photolithography,etching,thin film deposition,electroplating,bonding,thinning.This article briefly introduces the packaging technology of microsystems,and elaborates on the current development status and localization progress of its main process equipment.Through analysis and comparison,this article believes that microsystem packaging industry development has entered the rapidly growth period,and its required process equipment has relatively low requirements for process nodes but more needs in equipment types.It can be used as an important platform for impulsing localization of manufacturing equipment to vigorously develop,to enhance the tenacity and security level of the semiconductor industry chain and supply chain.
作者 罗天 刘佳甲 石倩楠 LUO Tian;LIU Jiajia;SHI Qiannan(CETC Electronic Equipment Group Co.,Ltd.,Beijing 100176,China)
出处 《电子工业专用设备》 2023年第6期1-9,共9页 Equipment for Electronic Products Manufacturing
关键词 工艺设备 3D堆叠 微系统集成 先进封装 通孔 微凸点 再布线 Manufacturing equipment 3D stacking Microsystem integration Advanced packaging TSV(Through silicon via) Bumping RDL(Re-distributed layer)
  • 相关文献

参考文献14

二级参考文献79

  • 1李传志.我国集成电路产业链:国际竞争力、制约因素和发展路径[J].山西财经大学学报,2020,0(4):61-79. 被引量:64
  • 2陆燕菲.集成电路封装技术现状分析与研究[J].电子技术(上海),2020(8):8-9. 被引量:14
  • 3WARREN W F, HA-AI N. Characterization of a copper pillar bump process [ C] //Proceedings of the 12'h IEEE Advanced Packaging Materials Symposium. San Jose, CA, USA, 2007: 208-213.
  • 4WEI K, BARRY L, JOHNSON T. Copper pillar bump technology progress overview [ J]. ICEPT-HDE, 2011 : 1133-1137.
  • 5SAITO K, SHOJI R. Bump structure, bump forming method and package connecting body: U.S. Patent, 6229220 [P]. 2001-05-08.
  • 6FRANCISCA T. Pillar connections for semiconductor chips and method of manufacture: U. S. Patent, 6578754 [P]. 2003-06-17.
  • 7YEOH A, CHANG M, PELTO C, et al. Copper die bumps (first level interconnect) and low-k dielectrics in 65 nm high volume manufacturing [ C] //Proceedings of the 56h IEEE Electronic Components and Technology Conference. San Diego, CA, USA, 2006: 1611-1615.
  • 8WANG H, CHEN S W. Electric current effect in flip chip solder joints [ J]. J Chin Inst Chem Engrs, 2006, 37 (2): 185-191.
  • 9IHARA Y, KANAZAWA T, KOBAYASHI T. Method of forming bumps by electroplating: U.S. Patent, 6413404 B1 [P]. 2002-07-02.
  • 10CHUNG, KUO E, TSENG M. Bump shape control on high speed copper pillar plating process in lead-free waferlevel packaging [ C ] //Proceedings of International Mi- crosystems, Packing, Assembly and Circuits Technology Conference. Taipei, China, 2009: 432-435.

共引文献84

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部