基于机器学习的高效率集成电路DFT技术研究

Research on High-Efficiency Integrated Circuit DFT Technology Based on Machine Learning

本文提出了一种基于机器学习的高效率集成电路可测性设计技术.该技术以自动收集的数据作为训练集,以决定系数为评价指标,为每类目标参数选择出最佳预测模型,并预测出基于不同配置参数的可测性设计结构所对应的目标参数,最后使用最优配置推断技术,以目标参数差值的加权和作为衡量指标,输出最优的可测性设计配置参数.实验数据表明,针对可测性设计技术中最重要的测试覆盖率参数,平均预测误差仅为0.0756%;根据目标参数差值的加权和的最小值情况,实现高效推断芯片可测性设计的最优配置参数.该技术的预测效果具有高可靠性,能够在保证高测试覆盖率的前提下,有效减少测试成本和面积开销等.

This paper proposes a high-efficiency design for test(DFT)technique for integrated circuits based on machine learning.The technology uses the automatically collected data as the training set and determination coefficient as the evaluation index,selects the best prediction model for each type of target parameters,and predicts the target parameters corresponding to the design for test structure based on different configuration parameters,and finally uses the optimal configuration.The inference technology uses the weighted sum of difference value of target parameters as a measure to output the optimal design for test configuration parameters.The experimental data shows that for the most important test coverage parameter in design for test technology,the average prediction error is only 0.0756%;according to the minimum value of weighted sum of difference value of target parameters,the optimal configuration parameters of the design for test can be efficiently inferred.The prediction effect of this technology has high reliability,and can effectively reduce the test cost and area overhead on the premise of ensuring high test coverage.