车规级LIN总线带隙基准设计

Band gap reference design for LIN bus

针对常规车载芯片中带隙基准电源抑制比(Power Supply Rejection Ratio,PSRR)差、电流驱动能力弱、功耗大等问题,提出了一种将输出的基准电压同时作为折叠式运放(Cascode)、尾电流管、缓冲器(Buffer)的新型动态偏置电路。基准电压经过该电路构成的负反馈,可以抑制电源电压或负载电流的波动。电路采用HH 90 nm CMOS工艺完成了建模,输出基准电压为1.18 V。仿真结果表明,在全工艺角下,输入电压可调范围为1.8~5 V,可驱动电流最高为8.2 mA;典型TT工艺角下,当电源电压为1.8 V时,静态电流为1.04μA,静态功耗为1.872μW;-40~+150℃的温度系数为6.6×10^(-6)/℃;空载频率为10 Hz时,PSRR为-89.6 dB。满足车规级局域互联网(Local Interconnect Network,LIN)总线对带隙基准性能的要求。

To address the problems of poor power supply rejection ration(PSRR),weak current driving ability and large power consumption in conventional on-board chips,a novel dynamic bias circuit was proposed,which used the output voltage reference as a folded cascode operational amplifier,a tail current tube and a buffer simultaneously.Through the negative feedback of the circuit,the reference voltage could suppress the fluctuation of the supply voltage or the load current.The circuit was modeled by HH 90 nm CMOS technology,and the output reference voltage was 1.18 V.The simulation results show that the input voltage is adjustable from 1.8 V to 5 V,and the maximum driving current is 8.2 mA at the whole process angle.At a typical TT process angle at supply voltage of 1.8 V,the total static current is 1.04μA with total static power consumption of 1.872μW.The temperature coefficient is 6.6×10-6/℃from-40℃to+150℃,and the PSRR is-89.6 dB at the no-load frequency of 10 Hz.It meets the requirements of LIN bus on bandgap benchmark performance.