基于CPLD的交换机电源时序研究

Research on power⁃on sequence of switch based on CPLD

针对传统硬件延迟电路的设计复杂且容易受外界环境影响,难以满足高性能交换机中多模块多电源上电时序要求严格的问题,采用国产安路的可编程逻辑器件和Verilog语言的有限状态机设计对交换机中CPU、FPGA和交换芯片进行上电时序控制。利用Modelsim对延迟模块和上电时序进行仿真验证。结果表明,上电时序控制设计的延迟为毫秒级别,状态机12个状态实现快速跳转,满足上电时序要求,并可以修改代码调整上电时序,适用于服务器、交换机等网络设备。

In view of the design of traditional hardware delay circuits is complex and easy to be affected by the external environment.It is difficult to meet the strict requirements of power-on sequence in high-performance switches with multi-module and multi-power supply.The power-on sequence control of the CPU,FPGA and switching chip is realized by using Anlogic CPLD and finite state machine in the Verilog language.Modelsim is used to simulate the delay module and power-on sequence.The results show that the design of the power-on sequence control satisfies ms level delay,the 12 states of the state machine can be quickly jumped,and the code can be modified to adjust the power-on sequence.It is applicable to network devices such as servers and switches by using above design.