低延迟抖动的证券行情数据解析系统设计与实现

Design and Implementation of a Securities Market Data Analysis System with Low Latency Jitter

为解决证券行情数据解析处理过程中纯软件解析高延迟、高抖动、易堵塞,FPGA硬件解析哈希存储冲突、维护成本高的问题,提出一种基于OpenCL和HLS的协同开发模式。通过HLS指令级并行流水优化提高并行度、KVS存储优化减少哈希冲突、二分查找并行优化降低延迟、动态键值表存储提升存储利用率等方式在Xilinx Alevo U50 FPGA加速卡中实现了低延迟、低抖动的证券行情数据解析。实验表明,在同时处理80支股票的情况下,相比CPU I9-9900X 10C20T,解析速度提升8倍,单条行情数据解析时间控制在189.8ns,抖动幅度维持在14ns以内,与传统的HDL硬件FPGA开发模式相比,开发效率提升3倍~4倍,能够更好地适应金融市场的迭代需求。

In order to solve the problems of high delay,high jitter,easy blockage,hashing conflict and high maintenance cost in the process of analysis and processing of stock market data by pure software,a cooperative development mode based on OpenCL and HLS is proposed.In Xilinx Alevo U50 FPGA accelerator card,low delay and low jitter are realized by HLS instruction level par⁃allel flow optimization to improve parallelism,KVS storage optimization to reduce hash conflict,binary search parallel optimization to reduce delay,and dynamic key-value table storage to improve storage utilization.The experiment shows that,compared with CPU I9-9900X 10C20T,the analysis speed is increased by 8 times,the analysis time of single market data is controlled at 189.8ns,and the jitter amplitude is maintained within 14ns.Compared with traditional HDL hardware FPGA development mode,the development efficiency is improved by 3~4 times.It can better adapt to the iterative needs of the financial market.