基于分段线性模型针对TLP瞬态干扰信号的芯片协同防护设计方法研究

Research on chip collaborative protection design method for TLP transient interference signals based on segmented linear model

集成电路芯片在高密度、小型化发展过程中产生了电磁兼容问题,为强化集成电路芯片对瞬态干扰信号的应对防护效果,可结合传输线脉冲(TLP)测试构建分段线性模型。文章首先对芯片应对瞬态干扰信号展开防护设计的现实需求进行分析,以CD4001BE芯片为例提出芯片TLP测试分段线性建模方式,总结瞬态电压抑制TVS二极管建模方法,并进一步展开芯片分段线性模型协同防护设计分析,旨为借助分段线性模型的方式控制芯片防护的设计时间与成本。

Integrated circuit chips have encountered electromagnetic compatibility issues in the process of high-density and miniaturization development.To enhance the protective effect of integrated circuit chips against transient interference signals,a segmented linear model can be constructed by combining transmission line pulse(TLP)testing.Based on this,this article first analyzes the practical needs of chip protection design for transient interference signals,taking the CD4001BE chip as an example,a segmented linear modeling method for chip TLP testing is proposed,and the modeling method for transient voltage suppression TVS diodes is summarized.Furthermore,the collaborative protection design analysis of chip segmented linear models is carried out to control chip protection according to design time and cost using the segmented linear model.