摘要
通信系统向小型化、高性能、集成化的快速发展对射频组件的体积和电性能提出了苛刻的要求。设计了一种X波段硅腔折叠基片集成波导(FSIW)环行器芯片。当基片集成波导(SIW)工作于主模时,将中央的对称面等效为虚拟磁壁,沿着窄边对电磁场进行多次折叠,形成FSIW。以该技术作为设计思路,提高空间利用率,实现了FSIW整体结构的小型化。将FSIW的优势融入环行器中心结设计,使设计的环行器芯片具有高功率容量、低插入损耗、体积小、质量轻的优点。基于微电子机械系统(MEMS)工艺,以高阻硅为衬底材料,制备了该硅腔FSIW环行器芯片,芯片整体尺寸为6.5 mm×6 mm×2.5 mm,工作频率为8.5~11.5 GHz,回波损耗>18.5 dB,带内插入损耗<0.4 dB,隔离度>20 dB。
The rapid development of communication systems towards miniaturization,high performance and integration has put forward strict requirements for the volume and electrical performance of RF components.A silicon cavity folded substrate integrated waveguide(FSIW)circulator chip for X-band was designed.When the substrate integrated waveguide(SIW)is working in the dominant mode,the central symmetry plane is equivalent to a virtual magnetic wall,and the electromagnetic field is folded multiple times along the narrow edge to form the FSIW.With the technology as the design idea,the space utilization rate was improved and the overall structure of FSIW was miniaturized.The advantages of FSIW were integrated into the design of the center junction of the circulator,so that the designed circulator chip has the advantages of high power capacity,low insertion loss,small volume and light mass.Based on micro-electromechanical system(MEMS)technology,with high-resistance silicon as substrate material,the silicon cavity FSIW circulator chip was fabricated.The overall chip size is 6.5 mm×6 mm×2.5 mm,the working frequency is 8.5-11.5 GHz,the return loss is>18.5 dB,in-band insersion loss is<0.4 dB,and isolation is>20 dB.
作者
高纬钊
杨拥军
汪蔚
翟晓飞
周嘉
Gao Weizhao;Yang Yongjun;Wang Wei;Zhai Xiaofei;Zhou Jia(The 13th Research Institute,CETC,Shijiazhuang 050051,China)
出处
《微纳电子技术》
CAS
2024年第3期120-125,共6页
Micronanoelectronic Technology