一种带Cache加速的HyperRAM控制器设计与验证

Design and verification of HyperRAM controller with Cache acceleration

针对目前可穿戴设备上对存储设备性能要求高、体积小、功耗低等问题,在FPGA上实现了一款可拓展的高性能HyperRAM控制器,并引入Cache缓存加速设计,以提高对频繁访问数据的命中率和优化存储器访问模式,实现更高速的数据传输和优化的系统性能。运用UVM验证方法学和FPGA进行验证,结果表明,带有Cache缓存的HyperRAM控制器相较于普通HyperRAM,在读写连续地址时性能提高61%,并具有较好的可靠性与有效性,可为嵌入式系统提供高效、灵活的存储器解决方案。

In allusion to the problems of high-performance requirements,small size and low power consumption of storage devices in wearable devices,a scalable high-performance HyperRAM controller is implemented on FPGA,and the design of Cache acceleration is introduced to improve the hit rate of frequently accessed data and optimize the memory access mode,so as to realize higher-speed data transmission and optimized system performance.By means of UVM verification methodology and FPGA verification,the results show that in comparison with ordinary HyperRAM,the performance of the HyperRAM controller with Cache cache is improved by 61% when reading and writing continuous addresses,and has good reliability and effectiveness,which can provide an efficient and flexible memory solution for embedded systems.