基于复合域的SM4两方协同加密算法的FPGA实现

FPGA Implementation of Bipartite Collaborative Encryption Algorithm for SM4 Based on Composite Field

针对SM4协同加解密算法软件实现效率低的问题,提出了一种基于复合域的SM4两方协同加解密算法的FPGA实现方案。为提高算法的实现速度,降低其硬件实现成本,将S盒中元素进行复合域分解并求逆。利用乘法三元组完成两方协同计算,并在FPGA上进行了验证。方案实现的最大时钟频率可达130.63Mhz,在不考虑双方通信时间的前提下,协同加/解密时间为7.852us,相较于软件实现快253.56倍,总逻辑单元占用数为7000个,相较于扩展的欧几里得方法占用减少了约51.9%,适用于实时性较高的场景。

To address the problem of low efficiency in software implementation of SM4 collaborative en-cryption and decryption algorithm,an FPGA implementation scheme of bipartite collaborative encryp-tion and decryption algorithm for SM4 based on composite field is proposed.To improve the implemen-tation speed and reduce the hardware cost,elements in the S-box are decomposed and inverted in the composite field.Multiplicative triples are utilized to realize bipartite collaborative computation,whose validity is verified on FPGA.With the proposed scheme,maximum clock frequency reaches 13063MHz,and when excluding the time for bipartite communication,the time for collaborative en-cryption/decryption is 7852us,which is 25356 times faster than that for the software implementation.Totally,7000 logic units are occupied,which is~519%lower than those for the extended Euclidean method.Experiment results indicate that the proposed scheme is suitable for the highly real-time sce-narios.