基于FPGA的高速模数转换器评估系统

Evaluation system of high-speed anolog to digital converter based on FPGA

设计并验证了一种基于现场可编程逻辑阵列(FPGA)的高速模数转换器(ADC)评估系统。基于FPGA设计了底层逻辑,根据不同的测试指标控制ADC的信号采集和数据转换,将模拟输入信号转换为数据存储到FPGA的分布式存储器(Block RAM)中,通过用户数据报协议(UDP)将数据传输到电脑端的基于MATLAB开发的上位机,由电脑中央处理器(CPU)负责处理计算数据并输出测试结果到用户界面上。以一款16位、采样率100 MS/s的ADC为例,以该评估系统对ADC的各项参数指标进行测试和分析。实验结果表明,该系统可以实现高速、高精度ADC的测试和评估。

A high speed anolog to digital converter(ADC)evaluation system based on field programmable logic array(FPGA)is designed and implemented.The logic codes are designed based on the FPGA,and the signal sampling and data transmission of ADC are controlled according to different test modes.The analog input signal is converted into digital data stored in the FPGA block RAMs,and transmitted through the user datagram protocol(UDP)to the upper computer designed in MATLAB,which processes the calculated data and output the test results to user.The parameters of a 16-bit ADC with a sampling rate of 100 MS/s are calculated and analyzed in the system.Experimental results show that this system can achieve high speed and high precision ADCs testing and evaluation.