一种可暂停的低功耗DMA控制器设计及验证

Design and Verification of a Pausable Low-Power DMA Controller

通过分析直接内存存取(DMA)控制器的工作原理和主要功耗来源,发现其在空闲状态时依然存在功耗较高的问题,为了解决空闲状态功耗损失问题以及满足DMA控制器实际传输过程中可能出现的暂停需求,提出了一种可暂停的低功耗DMA控制器设计方案。采用自适应时钟控制机制,通过加入时钟门控技术,根据DMA数据传输需求动态调整时钟,使DMA引擎模块功耗降低了62%。针对暂停需求,采用了一种可暂停的控制策略,通过加入暂停指令,实现对DMA传输的实时暂停和恢复,提高了DMA控制器的灵活性。为了保证DMA控制器功能的正确性和完备性,采用基于覆盖率驱动验证(CDV)的验证策略,划分DMA控制器的功能点,针对每个功能点编写测试用例,搭建通用验证方法学(UVM)仿真验证平台,进行大量随机测试和定向测试,给出了测试的结果以及完整的覆盖率分析结果。

By analyzing the working principle and main power sources of the direct memory access(DMA)controller,it is found that it still has the problem of high power consumption in the idle state.In order to solve the problem of power loss in the idle state and meet the pause requirement that may occur in the actual transmission process of the DMA controller,a design of pausable low-power DMA controller is proposed.The adaptive clock control mechanism is adopted.By adding the clock gating technology,the clock is dynamically adjusted according to the DMA data transmission requirement,and the power consumption of DMA engine is effectively reduced by 62%.For the pause requirement,a pausable control strategy is adopted.By adding a pausable instruction,the real-time pause and recovery of DMA transmission are realized,and the flexibility of the DMA controller is improved.In order to ensure the correctness and completeness of the DMA controller functions,a verification strategy based on coverage driven verification(CDV)is adopted to divide function points of the DMA controller and write test cases for each function point.A universal verification methodology(UVM)simulation and verification platform is built for a large number of random tests and directional tests,and the simulation results and complete coverage analysis results are given.