摘要
在大电流条件下,随着电流密度的增加,发射区结电流集边效应、基区电导调制效应、基区展宽效应会随之出现。基于研究单位的BCD工艺,在集成CMOS和DMOS的基础上集成功率纵向NPN双极晶体管用于输出。设计了75μm×4μm、50μm×6μm、30μm×10μm三种不同尺寸的发射极并进行TCAD仿真研究。在发射极面积相同的情况下,发射极长宽比越小,TCAD可观察到的电流集边效应越严重,最终流片并进行测试验证,得出75μm×4μm的细长结构尺寸能够提升晶体管在大电流下的放大能力,较30μm×10μm的结构提升约11.4%。
Under high current conditions,as the current density increases,the emitter current crowding effect,Webster effect,and Kirk effect will appear.Based on the BCD process of the research institute,power vertical NPN bipolar transistor is integrated into the integrated CMOS and DMOS for output.Three different sizes of emitters,75μmx4μm,50μmx6μm and 30μmx10μm,are designed and studied by TCAD simulation.With the same emitter area,the smaller the emitter aspect ratio is,the more serious the emitter current crowding effect can be observed by TCAD.The final flow and test validation conclude that the slender structural size of 75μmx4μm can enhance the amplification ability of transistors under high current by about 11.4%over the structure of 30μmx10μm.
作者
彭洪
王蕾
谢儒彬
顾祥
李燕妃
洪根深
PENG Hong;WANG Lei;XIE Rubin;GU Xiang;LI Yanfei;HONG Genshen(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)
出处
《电子与封装》
2024年第3期87-91,共5页
Electronics & Packaging