一款用于双向传输高速接口的阻抗校准电路

An impedance calibration circuit for bidirectional transmission of high-speed interface circuits

在具有双向传输功能的高速串行接口中,发射机输出端的两个电阻对电路性能有很大的影响。为提升电路在复杂环境中的工作性能,需要对电阻进行阻抗校准。传统的阻抗校准存在着功耗高、面积大、系统误差大、收敛时间长等缺点。针对上述问题,设计了一款用于双向传输高速串行接口的阻抗校准电路,通过共用电流源的方式有效地减小了阻抗校准电路的面积及功耗,并消除了电流源失配带来的系统误差;引入了带有失调消除的比较器,并对比较器中存在的开关管漏电及时钟馈通等效应进行优化,降低了校准电路的系统误差;使用了逐次逼近寄存器(Successive Approximation Register,SAR)逻辑对最佳的电阻校准控制码进行查找,从而减小了收敛时间。在SMIC 40 nm工艺上实现了一款高精度,低功耗,且可对两个电阻分别进行调节的阻抗校准电路。对两个待校准电阻进行蒙特卡洛分析,阻抗校准的3σ值分别为201.76 mΩ,198.80 mΩ,阻抗校准电路整体功耗为4.205 mW。

In the high-speed serial interface with bidirectional transmission function,the two resistors at the transmitter's output have a great impact on the performance of the circuit.In order to improve the performance of the circuit in complex environment,impedance calibration is required.The traditional impedance calibration has the drawbacks of high power consumption,large area,large system error and long convergence time.To solve the above problems,this paper designs an impedance calibration circuit for two-way transmission of high-speed serial interface.By sharing current sources,the area and power consumption of the impedance calibration circuit are effectively reduced,and the system error caused by current source mismatch is eliminated.A comparator with misalignment elimination is introduced,and the system error of the calibration circuit is reduced by optimizing the leakage of the switch tube and the clock feed-through in the comparator.Successive Approximation Register(SAR)logic is also used to find the best resistance calibration control code,which reduces the convergence time.A high precision,low power consumption impedance calibration circuit is implemented in SMIC 40 nm process,which can adjust two resistors separately.The two resistors to be calibrated are analyzed by Monte Carlo,and the impedance calibration 3σvalues are 201.76 mΩand 198.80 mΩ,respectively.The overall power consumption of the impedance calibration circuit is 4.205 mW.