基于全数字锁相环优化的快速跳频技术研究

Research on fast frequency hopping technology based on all digital phase locked loop optimization

针对全数字锁相环(ADPLL)在跳频时间、信号质量、频率步进等方面的不足,对ADPLL的环路结构和数字锁频算法进行了优化,设计了一种新型全数字锁相环结构。该结构采用快速频率电压转换器(FVC)替代ADPLL中的数字鉴频鉴相器和数字滤波器。FVC通过将参考频率进行倍频,再对反馈频率进行计数,直接计算出输出频率值,进而确定输出频率与目标输出频率的误差,通过建立频率误差与调整电压的函数关系,控制输出频率的快速锁定,实现了小步进、高质量的快速合成频率输出。最后,通过仿真和实测验证了新型全数字锁相环结构的可行性。实测结果表明,该技术合成的频率近端杂散为-87 dBc,频率步进最小可以达到191 Hz,跳频时间最小为3.9μs。

Aiming at the shortcomings of all digital phase-locked loop(ADPLL)in terms of frequency hopping time,signal quality,frequency stepping,the loop structure and digital phase-locked algorithm of ADPLL are optimized,and a new type of all digital phase-locked loop structure is designed.This structure adopts a Fast Frequency to Voltage Converter(FVC)to replace the digital frequency and phase discriminator and digital filter in ADPLL.FVC calculates the output frequency value directly by doubling the reference frequency and counting the feedback frequency,thereby determining the error between the output frequency and the target output frequency.By establishing a functional relationship between frequency error and voltage adjustment,FVC controls the fast locking of the output frequency,achieving small frequency steps and high-quality fast synthesis frequency output.Finally,the feasibility of the new all digital phase-locked loop structure has been verified through simulation and actual measurement.The actual test results show that the frequency near end spurious synthesized by this technology is-87 dBc,the minimum frequency step can reach 191 Hz,and the minimum frequency hopping time is 3.9μs.