基于视觉强化学习的数字芯片全局布局方法

Visual-based reinforcement learning for digital chip global placement

在数字芯片后端设计中,全局布局需要同时兼顾线长与合法化,是一个组合优化问题。传统的退火算法或者遗传算法耗时且容易陷入局部最优,目前强化学习的解决方案也很少利用布局的整体视觉信息。为此,提出一种融合视觉信息的强化学习方法实现端到端的全局布局。在全局布局中,将电路网表信息映射为多个图像级特征,采用卷积神经网络(convolutional neural network,CNN)和图卷积网络(graph convolutional network,GCN)将图像特征和网表信息相融合,设计了一整套策略网络和价值网络,实现对全局布局的全面分析和优化。在ISPD2005基准电路上进行实验,结果证明设计的网络收敛速度加快7倍左右,布局线长减少10%~32%,重叠率为0%,可为数字芯片全局布局任务提供高效合理的方案。

In the back-end design of digital chips,it needs to consider both wire length and legalisation during global placement.Global placement represents a combinatorial optimization problem.Traditional annealing algorithms or genetic algorithms consume a significant amount of time and are susceptible to entering local optima.Current reinforcement learning solutions seldom leverage the overall visual information of the placement.Therefore,this paper proposed a reinforcement learning method that incorporated visual information to attain end-to-end global placement.During the global placement,it mapped the circuit netlist information into multiple image-level features,and utilized CNN and GCN to merge the image features with the netlist information.It employed a complete set of strategy networks and value networks to conduct comprehensive analysis and optimization of the global placement.Experiments on the ISPD2005 benchmark circuit demonstrate that the designed networks accelerate the convergence speed by approximately 7 times,reduce the placement wire length by 10%to 32%,and achieve a 0%overlap rate.This approach offers an efficient and rational solution for the global placement task of digital chips.