国产FPGA上通信基带发端算法设计和系统实现

Design and implementation of the baseband algorithm on domestic FPGA

该文针对国产FPGA上通信基带算法及相关信号处理算法IP核匮乏现状,设计了基于紫光Logos系列FPGA器件的通信基带发端算法;在紫光FPGA缺乏FIR IP核的情况下,经优化设计实现了仅用7个乘法器的60阶FIR成型滤波器;搭建收发测试环境对设计的发端系统进行了测试。测试结果表明,所设计的基于正交调制的发端基带算法和基带系统性能达到主流水平的技术指标要求,实现了首批通信算法和通信系统在国产FPGA器件上的应用。

[Objective]With the rapid rise and wide application of domestic field-programmable gate array(FPGA)devices,they have increasingly become central to various professional fields.However,despite the growing popularity of domestic FPGA devices,there is a relative scarcity of IP cores that implement the communication baseband algorithms and related signal processing algorithms.This situation limits the application and development of domestic FPGAs in the communication field.Addressing this gap,this paper aims to design and implement an IP core for communication baseband algorithms and related signal processing algorithms on a domestic FPGA.[Methods]This is done to maximize the potential of domestic FPGAs in the communication field.The paper covers the entire workflow of baseband processing,including source generation,constellation mapping,and shape filtering.In the source generation module,a pseudorandom sequence generator(PRBS)ensures the randomness and stability of the signal.For constellation mapping,quadrature amplitude modulation is utilized as it effectively enhances the signal’s transmission efficiency while maintaining its quality.The design and optimization of the filter structure are based on the observation that many zeros exist between two valuable data points in the transmitted data,resulting in 0 when multiplied by the filter coefficient.This paper discusses and designs an algorithm structure for the FIR direct filter,which consists of 60 shift registers and 61 multipliers.This algorithm can dynamically move each nonzero input data in the corresponding row and multiply these moving data by the coefficients corresponding to each row of the filter.Moreover,this algorithm structure cycles every ten clock cycles,ensuring the stability and continuity of the algorithm.As a consequence,through this structure,the function of a 60-order root-raised cosine filter can be realized using only seven multipliers.In the case of an FPGA lacking an FIR IP core,the optimized design can simultaneously process nonzero input data.To meet the requirements of the I and Q outputs,we utilized 14 APM resources,each sized at 18×18.Compared with the 122 APM resources required before optimization,the impact of this structural design optimization is significant.It reduces the number of 18×18 multiplier resources used by over 86%.[Results]Functional simulation results show that through fine algorithm design and optimal allocation of FPGA resources,we have successfully realized efficient and stable baseband signal processing on domestic FPGA devices.Furthermore,a test environment was established to evaluate the designed originating system.The results confirm that the originating baseband algorithm,based on orthogonal modulation,along with key performance indicators such as system performance and error vector amplitude(EVM),meet the requirements of mainstream technical indicators.These accurate results not only prove the accuracy and robustness of our design but also reflect the efficient management of hardware resources.[Conclusions]Through this design,we have paved the way for the application of the first batch of communication algorithms and communication systems in domestic FPGA devices.