概率计算及混合概率计算

Stochastic Computing and Hybrid Stochastic Computing

非位置概率数的计算机制已经成为边缘计算片上系统的新范式.本文介绍了概率计算(stochastic computing)的起源、发展和目前国内外的研究现状.针对传统概率计算存在诸如计算时延长、脉冲串信息携带效率低等问题,本文提出了二进制数-概率脉冲串混合编码的混合概率数概念,并从数的表示机理上阐释了二进制数、概率数和混合概率数的数理关系,进而揭示了混合概率计算所具备的低时延、高算力和高能效比的计算特点.本文基于40 nm CMOS工艺设计混合概率深度神经网络,该神经网络芯片在内核面积仅0.73 mm×0.73 mm的条件下,设计4544个乘累加(MAC)单元.在时钟频率400 MHz条件下,总功率为102.3 mW,其中动态功耗仅97μW.通过ASIC芯片的实验测试表明,混合概率计算作为一种全新的颠覆性计算范式,与其他确定性、可扩展和全并行等概率计算方案相比,其能效比分别提高了50倍、2.5倍和3.26倍.

The calculation principle of non-positional stochastic number(SN)is a promising technique for realizing high-performance computing owing to its extremely low hardware cost.This paper introduces detailly the origin,develop⁃ment process and the domestic and foreign development present situation.However,a disadvantage of stochastic bitstream is that the computing latency,and information-carrying efficiency and so on.We presented a hybrid stochastic computing(HSC)based on a hybrid bitstream to solve these problems,which achieves a lower hardware cost,better accuracy,and fast⁃er speed.The HSC neural networks is fabricated by 40 nm low-power CMOS process,with a core area of 0.73 mm×0.73 mm,power of 102.3 mW and clock of 400 MHz,which has 4544 multiply and accumulation(MAC).The proposed Hybrid stochastic computing is tested by FPGA and ASIC.Compared with other stochastic computing method,the method proposed gains 50×,2.5×,and 3.26×energy efficiency than other methods of traditional stochastic computing.