Cryo-CMOS modeling and a 600 MHz cryogenic clock generator for quantum computing applications

The development of large-scale quantum computing has boosted anurgent desire for the advancement of cryogenic CMOS(cryo-CMOS),which is a promising scalable solution for the control and read-out interface of quantum bits.In the current work,180 nm CMOS transistors were characterized and modeled down to 4 K,and the impact oflow-temperature transistor performance variations on circuit designwas also analyzed.Based on the proposed cryogenic model,a 180 nmCMOS-based 450 to 850 MHz clock generator operating at 4 K forquantum computing applications was presented.At the output frequency of 600 MHz,it achieved<4.8 ps RMS jitter with 30 mWpower consumption(with test buffer),corresponding to a−211.6 dBjitter-power FOM,which is suitable for providing a stable clock signalfor the control and readout electronics of scalable quantum computers.