一种基于新型低功耗开关策略的10 bit 120 MS/s SAR ADC

A 10 bit 120 MS/s SAR ADC Based on a Novel Low Power Switching Strategy

设计了一种10 bit 120 MS/s高速低功耗逐次逼近模数转换器(SAR ADC)。针对功耗占比最大的CDAC模块,基于电容分裂技术并结合C-2C结构,提出了一种输出共模保持不变的双电平高能效开关控制策略;在降低CDAC开关功耗的同时,摆脱了CDAC开关过程中对中间共模电平的依赖,使得该结构适用于低电压工艺。在速度提升方面,控制逻辑使用异步逻辑进行加速;比较器采用一种全动态高速结构,在保证精度的前提下其工作频率达到3 GHz;CDAC中插入冗余位,以降低高位电容对充电时间的要求。所设计的SAR ADC使用40 nm CMOS工艺实现,采用1.1 V低电压供电。在不同工艺角下进行性能仿真,结果显示,在120 MHz采样率下,有效位数为9.86 bit,无杂散动态范围为72 dB,功耗为2.1 mW,优值为18.9 fJ/(conv·step)。

A 10 bit 120 MS/s high speed and low power successive approximation analog-to-digital converter(SAR ADC)was designed.To address the power consumption of the capacitive digital-to-analog converter(CDAC)module,a dual-level high efficiency switch control strategy that maintains common-mode output was proposed,utilizing capacitive splitting technique combined with a C-2C structure.This structure not only reduced the switching power consumption of CDAC but also eliminated the dependence on the intermediate common-mode level during the CDAC switching process,making it suitable for low voltage processes.In terms of improving the speed,ADC used asynchronous logic for acceleration in its control logic.The comparator adopted a fully dynamic high speed structure,which could achieve a working speed of 3 GHz while ensuring accuracy.For CDAC,redundant bits were inserted to reduce the charging time requirements of high order capacitors.The SAR ADC was implemented in a 40 nm CMOS process and operated at a low voltage of 1.1V.Performance simulations were conducted under various process corner conditions.The results show that at a sampling rate of 120 MHz,the effective number of bits(ENOB)is 9.86 bit,the spurious-free dynamic range(SFDR)is 72 dB,the power consumption is 2.1 mW,and the figure of merit(FOM)is 18.9 fJ/(conv·step).