一种基于局部间断Galerkin方法的IC互连线电容提取策略

An Interconnect Capacitance Extraction Strategy of Integrated Circuit Based on Local Discontinuous Galerkin Method

求解椭圆方程的局部间断Galerkin(LDG)方法具有精度高、并行效率高的优点,且能适用于各种网格。文章提出采用LDG方法来求解IC版图中电势分布函数满足的Laplace方程,从而给出了一个提取互连线电容的新方法。该问题的求解区域需要在矩形区域内部去掉数量不等的导体区域,在这种特殊的计算区域上,通过数值测试验证了LDG方法能达到理论的收敛阶。随着芯片制造工艺的发展,导体尺寸和间距也越来越小,给数值模拟带来新的问题。文章采用倍增网格剖分方法,大幅减小了计算单元数。对包含不同数量和形状导体的七个电路版图,用新方法提取互连线电容,得到的结果与商业工具给出的结果非常接近,表明了新方法的有效性。

The local discontinuous Galerkin(LDG)method has the advantages of high order of accuracy and efficiency of parallel implementation,and can work on many kinds of meshes.In this paper,the LDG method was adopted to solve the Laplace equation that governs the electric potential function for an integrated circuit layout,resulting in a new method to extract the capacitance of interconnects.The computational domain of this problem was derived by removing multiple conductor regions from a rectangular domain.For such special computational domains,it was numerically verified that the LDG method can achieve the theoretical convergence order.As the chip manufacturing process improves,the size and spacing of the conductors are getting smaller and smaller,which brings new difficulties to numerical simulations.In this paper,gradually coarsened meshes were used to significantly reduce the computational elements.The new method was applied to extract interconnect capacitance for seven circuit layouts that contain different numbers and shapes of conductors.The results are very close to the ones given by a commercial tool,indicating the effectiveness of the new method.