基于现场可编程门阵列的矩阵求逆算法设计

Design of Matrix Inversion Algorithm Based on Field Programmable Gate Array

由于自适应抗干扰算法在更新最优权值时存在时间延时,导致很难满足动态环境下的权值更新率要求。针对该情况已有学者对如何实现快速采样矩阵求逆算法进行研究,但仍存在只适用于低维矩阵,且权值更新率慢的问题。为解决上述问题,提出了一种基于Cholesky分解的采样矩阵求逆算法实现架构。该实现架构主要包括协方差矩阵计算模块、Cholesky分解模块、计算下三角矩阵L的逆矩阵模块、三角矩阵相乘和权值计算模块。设计采用流水线加状态机实现结构有效地解决了因高阶采样矩阵求逆运算量大产生的权值更新率慢的问题。仿真结果表明,在现场可编程门阵列(field programmable gate array,FPGA)的硬件平台上,对于56阶采样矩阵,在100 MHz工作频率下,一次权值的更新时间仅需要1.2 ms。本文所提的实现架构为自适应抗干扰快速求解权值提供了一种切实可行的解决方案,对存在类似需求的权值求解系统具有一定的参考价值。

Because the adaptive anti-jamming algorithm has a time delay when updating the optimal weight,it is difficult to meet the weight update rate requirements in a dynamic environment.In view of this situation,scholars have studied how to implement the fast sampling matrix inversion algorithm,but there is still a problem that it is only applicable to low-dimensional matrices and the weight update rate is slow.In order to solve the above problems,a sampling matrix inversion algorithm implementation architecture based on Cholesky decomposition was proposed.The implementation architecture mainly includes a covariance matrix calculation module,a Cholesky decomposition module,an inverse matrix module for calculating the lower triangular matrix L,a triangular matrix multiplication and weight calculation module.This design adopts a pipeline and state machine implementation structure,which effectively solves the problem of slow weight update rate caused by the large inverse operation of the high-order sampling matrix.The simulation results show that on the hardware platform of field programmable gate array(FPGA),for the 56-order sampling matrix,the update time of a weight only needs 1.2 ms under the working frequency of 100 MHz.The implementation architecture proposed in this article provides a practical and feasible solution for adaptive anti-jamming to quickly solve weight values,and has certain reference value for weight solving systems with similar requirements.