高速通信系统中并行CRC计算及电路实现

Parallel CRC calculation and circuit implementation inhigh speed communication systems

针对高位宽数据情况下的循环冗余校验码(Cyclic Redundancy Code, CRC)电路计算工作频率较低以及资源占用过多的问题,设计并实现了一种并行CRC计算方法。该方法将CRC计算拆分为数据CRC计算和余数CRC计算两个部分,余数CRC计算由多个余数CRC计算模块级联完成,数据CRC计算模块由固定逻辑表达式实现,对二者计算结果做模二加法即得到CRC计算结果。根据数据长度选择相应的数据CRC计算模块和余数CRC计算模块的组合,以适应高位宽可变数据长度的CRC计算。以100 Gbps远程直接数据存取(Remote Direct Memory Access, RDMA)通信系统中的1 024 bits数据位宽CRC-32的计算为例,在VCU118开发板上实现了该算法的硬件电路。实验结果表明,所提设计仅使用4 760个查找表和2 658个触发器,整个系统带宽最高可达97.85 Gbps,最高工作频率可达326 MHz。与其他相关方法相比,提出的方法具有较高的工作频率且资源占用较少。

A parallel cyclic redundancy code(CRC)calculation method is designed and implemented for the CRC calculation circuits in case of high bit-width data,which has the problems of low calculation working frequency and excessive resource consumption.The method splits the CRC calculation into two parts:the data CRC calculation and the remainder CRC calculation.The remainder CRC calculation is accomplished by multiple remainder CRC calculation modules connected in cascade,and the data CRC calculation module is realized by a fixed logic expression,and the results of the two calculations are obtained by doing the modulo-two addition.The combination of data CRC calculation module and residue CRC calculation module can be selected by data length to adapt to the CRC calculation of variable data length with high bit width.Taking the CRC-32 calculation of 1024 bits data in 100 Gbps remote direct memory access(RDMA)communication system as an example,the hardware circuit of the algorithm is realized on the VCU118 development board.The experimental results show that the proposed design uses only 4760 lookup tables and 2658 flip-flops,and the whole system bandwidth can reach up to 97.85 Gbps,and the maximum operating frequency can reach up to 326 MHz.Compared with other related methods,the proposed method has a higher operating frequency and less resource consumption.