一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

A Low Power Consumption Sigma⁃Delta ADC with a 1 to 128 Variable Gain Amplifier

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

A low power consumption Sigma⁃Delta analog⁃to⁃digital converter(ADC)chip was de⁃signed and fabricated to meet the requirements of low power consumption in sensor applications.The ADC employed a first⁃order fully differential switched⁃capacitor Sigma⁃Delta modulator,and integrated a pro⁃grammable gain amplifier(PGA)and bandgap reference.A 1.5 bit quantization structure was used,re⁃ducing quantization error by 3 dB compared with the 1 bit quantization structure.Optimized feedback cir⁃cuits were employed to reduce errors introduced by capacitor mismatch.The rail⁃to⁃rail operation amplifier circuit topology adopted by PGA enables a wide range of chip voltage adaptation.Based on the 180 nm CMOS process,the design and fabrication of this ADC were carried out.Test results indicate that at a sampling frequency of 512 kHz and oversampling rate(OSR)of 256,the peak signal⁃to⁃noise and distor⁃tion ratio(SNDR)and effective number of bits(ENOB)of the Sigma⁃Delta ADC are 75.29 dB and 12.21 bit,respectively,and the power consumption of the chip is only 0.92 mW.The chip can operate in a wide power supply voltage range of 2.3-5.5 V,achieving a maximum gain of 128 V/V.It is suitable for signal measurement applications of small sensors,meeting the requirements of low power consumption and high accuracy for small sensors.