环栅晶体管制备中SiGe选择性刻蚀技术综述

An Overview of SiGe Selective Etching Technology Used for the Preparation of Gate-All-Around Transistor

环栅(Gate-all-around,GAA)晶体管是3 nm以下节点替代现有鳍式晶体管(FinFET)最有竞争力的器件结构,能有效改善器件尺寸不断微缩带来的短沟道效应。与FinFET相比,GAA器件制备的工艺流程中内侧墙制备和沟道释放是新引入的工艺模块,均需要SiGe选择性刻蚀技术。工艺要求SiGe作为牺牲层被选择性刻蚀去除,且尽可能减少对Si沟道的损伤。本文对环栅晶体管制备工艺中所需的SiGe选择性刻蚀技术进行了综述,主要分析了器件结构的发展趋势及SiGe选择性刻蚀的应用,并分类综述了常规SiGe选择性刻蚀方法以及新型选择性刻蚀技术的发展历程,分析了各种技术的优点和不足。最后对SiGe选择性刻蚀技术面临的挑战进行了分析,并对其未来可能的发展趋势进行了展望。

Gate-all-around(GAA)transistors are the most competitive device structure to replace existing fin field effect transistors(FinFET)below the sub-3 nm node,effectively improve the short-channel effect caused by the continuous shrinking of device size along Moore s Law.In the process flow of GAA device preparation,inner spacer preparation and channel release are newly introduced process modules relative to FinFET,and both require SiGe selective etching technology.SiGe is required to be removed as a sacrificial layer by selective etching with as little damage as possible to the Si channel.This paper presents a review of the SiGe selective etching techniques required in the gate-all-around(GAA)transistor fabrication process.Firstly,we analyze the development trend of device structure and the application of SiGe selective etching.Secondly,the development of conventional SiGe selective etching methods and new selective etching techniques are categorized and reviewed.After that the advantages and shortcomings of each technique are summarized.Finally,this study analyzes the challenges faced by SiGe selective etching technology,and prospects the possible future development trends.