摘要
嵌入式SiGe(eSiGe)外延生长(EPI)广泛应用于先进的28 nm及以下CMOS器件的PMOS Source/Drain(S/D)部分构建技术中。在S/D端引入SiGe,同时加入一定量的Boron(SiGe:B),可以有效地给器件沟道(channel)提供应力,提高载流子通过速率,改善器件性能。随着逻辑功率芯片工艺节点推进,如何有效地控制外延生长形貌、Ge/B含量等诸多因素带来的缺陷和应力松弛问题变得越来越具有挑战性和关键性。
Embedded SiGe(eSiGe)epitaxial growth(EPI)is widely used in the PMOS Source/Train(S/D)construction technology of advanced CMOS devices at 28 nm and below.Introducing SiGe at the S/D end and adding a certain amount of Boron(SiGe:B)can effectively provide stress to the channel of the device,improve the carrier passing rate,and improve device performance.With the advancement of logic power chip technology nodes,it has become increasingly challenging and critical to effectively control the defects and stress relaxation caused by various factors such as epitaxial growth morphology and Ge/B content.
作者
聂望欣
NIE Wangxin(China Nanhu Academy of Electronics and Information Technology,Jiaxing 314002,China)
出处
《智能物联技术》
2023年第5期6-9,共4页
Technology of Io T& AI
关键词
外延生长
形貌控制
缺陷控制
器件性能
epitaxial growth
morphological control
defect control
device performance
