一种快速锁定的数字延迟锁相环设计

A Design of Fast-locking Digital Delayed Phase-Locked Loop

在高速存储器中,需要保证输出时钟和系统输入时钟同步,所以要用到锁相功能,传统的锁相环(Phase-Locked,PLL)会有抖动累积等问题,而传统延迟锁相环(Delay-Locked Loop,DLL)由于采用延迟链结构,使其理论锁定时间较长。本文提出一种快速锁定的DLL,采用两个锁存器形成波形相位判断机,形成状态字,用以实现锁定窗口判定机制,利用时钟脉冲实现延迟链的左右双向移动,从而实现更快的锁定。仿真结果表明,本设计能够在15个周期内完成输入时钟和输出时钟的相位同步,锁定范围是200 MHz~600 MHz,最大时间抖动为50ps。

In high-speed memory,it is necessary to use the phase-locked function to ensure that the output clock and the system input clock are synchronized.The traditional phase-locked loop(PLL)will have problems such as jitter accumulation,while the traditional delay-locked loop(DLL)has a long theoretical locking time due to the delay chain structure.In this paper,a fast-locking DLL is proposed,which uses two latches to form a waveform phase judgment machine and form a status word to realize the locking window judgment mechanism.The design uses the clock pulse to realize the left and right bidirectional movement of the delay chain,so as to achieve faster locking.The simulation results show that the circuit can complete the phase synchronization of the input clock and the output clock within 15 cycles,with the locking range of 200 MHz~600 MHz and the peak-to-peak jitter is 50ps.