一种单总线接口逻辑芯片验证方法

A method for verifying the logic chip of a single bus interface

单总线接口逻辑芯片的每项命令功能运行,必须通过单总线接口实现,所以单总线接口的通信稳定性、健壮性尤为重要,本文介绍一种既能够对逻辑芯片单总线接口各种边界时序的通信稳定性进行验证,也能够对逻辑芯片的所有命令功能进行验证的验证方法。本文中的单总线接口边界时序验证遍历了Start信号边界和0/1信号边界的所有组合;本文采用了分层设计的结构,同时,验证命令的运行方式既验证了用户实际使用场景,也验证了各条命令间的逻辑联系,还能够实现长时间稳定性验证。

Each command function of the single bus interface logic chip must be implemented through the single bus interface,so the single bus interface communication stability and robustness are particularly important.This paper introduces a verification method,which can verify the communication stability of all kinds of boundary time series of the single bus interface of the logic chip and verify all command functions of the logic chip.The single-bus interface boundary timing verification traversal is presented in this paper.All combinations of Start signal boundary and 0/1 signal boundary are obtained..This paper adopts the structure of layered design;In this paper,the running mode of the verification command not only verifies the actual usage scenario of the user,verifies the logical relationship between each command,but also can realize the long-term stability verification.