基于JESD204B确定性延迟的多芯片同步自动校正设计

Design of Multi-Chip Synchronization Automatic Correction Based on JESD204B Deterministic Delay

针对高速模数转换器JESD204B接口多芯片同步系统在稳定性、可靠性和可重复性上面临的确定性延迟问题,提出一种解决方案。该方案基于子类1同步原理,通过自动校正参考时钟相对于器件时钟的建立保持时间,以及利用确定性延迟原理实现可重复确定性延迟的自动校正。采用可调SYSREF延迟与模数转换器内部检测机制自动校正技术,确定最优延迟时刻,实现多片模数转换器的固定相位采样。在可编程逻辑芯片接收端自动校正数据到达与本地多帧时钟的相对位置,从而建立稳定、可重复的确定性延迟。本设计有助于多芯片同步系统更好地应对恶劣环境和自身敏感的延迟变化。

Aiming at the problem of deterministic delay in stability,reliability and repeatability of high-speed analog-to-digital converter JESD204B interface multi-chip synchronization system,a solution scheme is proposed.Based on the synchronization principle of subclass 1,the scheme can automatically correct the repeatable deterministic delay by automatically correcting the setup and hold time of reference clock relative to the device clock and using the deterministic delay principle.The technology of adjustable SYSREF delay and automatic correction of internal detection mechanism of analog-to-digital converter is adopted to determine the optimal delay time and realize fixed phase sampling of multi-chip analog-to-digital converter.At the receiving end of the programmable logic chip,the relative position of data arrival with the local multi-frame clock is automatically corrected,thus establishing a stable and repeatable deterministic delay.The design is helpful for multi-chip synchronization system to better cope with harsh environment and self-sensitive delay changes.