DDR5 SPD接口通信研究

Research on DDR5 SPD Interface Communication

DDR SPD是获取内存参数,进行内存训练的关键器件。目前DDR SPD已经演进到第5代,由传统的I^(2)C接口升级为I^(3)C接口。该文针对目前处理器需要集成的I3C模块,介绍了模块的设计组成及逻辑实现原理。同时,在FPGA平台上进行了仿真验证,通过连接实际的DDR5 RDIM M,完成了对DIM M上的SPD5118器件及其LSCL/LSDA总线上挂载的其他设备的访问,验证了模块的基本数据通路功能,对于总线IO PAD的适用进行探索。

DDR SPD is a key device for obtaining memory parameters and conducting memory training.At present,DDR SPD has evolved to the 5th generation,upgrading from the traditional I^(2)C interface to the I^(3)C interface.This article introduces the design composition and logical implementation principle of the I3C module that currently needs to be integrated into processors.At the same time,simulation verification was conducted on the FPGA platform.By connecting the actual DDR5 RDIMM,access to SPD5118 devices on the DIMM and other devices mounted on the LSCL/LSDA bus was completed,and the basic data path function of the module was verified.The applicability of bus IO PAD was explored.