忆阻器三值逻辑电路设计中信号衰减问题的优化

Optimization of signal degradation problems in the design of memristor ternary logic circuits

提出一种基于忆阻器三值逻辑电路的优化方案.针对组合逻辑电路中忆阻器多个级联门导致输出信号退化和逻辑结果错误等问题,利用忆阻器作为主流器件设计缓冲器,对逻辑电路的性能改善明显.利用LTspice对所提出的缓冲器在三值数据比较器、乘法器、减法器以及编码器等电路中进行有效性验证.改进后的电路输出信号高电平约2 V,低电平约为0,可为后续研究复杂逻辑运算、大规模忆阻器的三值以及多值电路的设计提供新思路.

The paper presented an optimization of a memristor-based ternary logic circuit,in order to address the problems of multiple cascaded gates of memristor in combinational logic circuits,which lead to degraded output signal and logic result errors,the design of buffer used memristor as a dominate devices,which had significantly improved the logic circuit results.The proposed buffer with a ternary data comparator,multiplier,subtractor and encoder was verified by LTspice,which output signal of the improved circuit was about 2 V at the high level and 0 at low level.The results provide new ideas in the future study of complex logic operations,large-scale memristor ternary and multiple-value circuits design.