Ad Hoc网络中基于DTN机制的队列管理器设计

Queue Manager Circuit Design Based on DTN in Ad Hoc Networks

设计了一种将延迟容忍网络(Delay Tolerance Network,DTN)技术应用于自组织(Ad Hoc)网络的队列管理器(Queue Manager,QM)。该管理器由自由指针QM、多队列消息存储器、DDR3、输入接口状态机、重发接口状态机和输出接口状态机等模块组成,能根据用户需求区分不同业务流,并对指定数据进行基于完整消息的多次重传。具有结构简单、低时延、资源动态共享和便于数据管理的特性。分析了QM的具体结构和工作流程,并进行了仿真验证。QM基于Xilinx xc7z100ffg900-2 FPGA平台实现,采用ModelSim SE-64 10.6d进行仿真分析。结果表明,该队列管理器能满足延迟容忍网络中交换节点对消息管理的需求。

A QM(Queue Manager)that applies DTN(Delay Tolerant Network)techniques to Ad Hoc networks is designed.The manager consists of modules such as free pointer QM,multi-queue message memory,DDR3,input interface state machine,retransmission interface state machine and output interface state machine,etc.It can distinguish different service flows according to user requirements and carry out multiple retransmissions of specified data based on complete messages.It is characterized by simple structure,low delay,dynamic resources sharing and easy data management.The specific structure and workflow of QM are analyzed and validated through simulation.QM is implemented on the Xilinx xc7z100ffg900-2 FPGA platform and is simulated and analyzed using ModelSim SE-6410.6d.The results demonstrate that the queue manager meets the message management needs of exchanging nodes in delay tolerant networks.