基于片上时钟控制器的电路全速测试设计与实现

Design and Realization of At-speed Test for the Chip Based on On-chip Clock Controller

阐述芯片在55nm CMOS工艺下,基于片上时钟控制器,对电路的数字逻辑部分、嵌入式存储器部分分别进行全速测试的可测性设计。通过对芯片全速测试的可测性设计和验证,测试时间得到缩短。

This paper expounds the on-chip clock controller based on 55nm CMOS process by inserted user-defined OCC controllers,in which the digital logic part and embedded memory part of the circuit could be tested at full-speed.After the at-speed design for test of the chip,the test time is reduced.