一种基于布斯算法的容错乘法器设计

Design of Error-tolerant Booth Multipliers for Computing

数字电路算法的容错设计是通过降低电路运算精度达到低功耗、高速率和低延时目的。本文基于布斯乘法器编码算法对乘法器电路进行了容错设计,提出了一种容错的高速低功耗乘法器,并对其容错性能进行了分析;还给出了在45nm特征尺寸、室温和常态仿真条件下功耗、面积和延时的仿真结果,证实了本文提出的容错乘法器在硬件表现上有很大的改进。最后,在图像处理中使用本文提出的容错乘法器模型进行仿真实验,结果证实了本设计具有广泛的应用前景。

Error tolerant computing is an attractive design methodology to achieve low power,high performance and low delay by relaxing the requirement of accuracy.In this paper,error tolerant Booth multipliers are designed based on radix-4 modified Booth encoding algorithms.The error characteristics are also analyzed with respect to the so-called approximation factor that is related to the inexact bit width of the Booth multipliers.Simulation results at 45 nm feature size in CMOS for power,area and delay consumption are also provided;they confirm that the proposed designs significantly improve over existing error tolerant and exact designs with respect to these figures of merit while incurring very modest errors.Case studies for image processing show the validity of the proposed error tolerant Booth multipliers.