基于时钟抖动流水线结构的高效率真随机数发生器

An efficient true random number generator based on jitter pipeline

现代加密系统对密钥随机性的需求不断增加。使用时序抖动、热噪声、亚稳态等作为熵源的真随机数发生器,因其可以提供高质量的随机性成为该领域的研究热点。因此,提出一种可配置、轻量级、高效率的真随机数发生器。该发生器使用基于随机数学模型的设计方法,由差分构架的两级时钟抖动流水线组成。第一级流水线中两个环形振荡器在规定时间内累积抖动,第二级流水线利用近似相同的两个环形振荡器的微小周期差构建时间数字转换器,对第一级输出的高斯抖动进行量化,通过数字化模块输出随机比特。在时间数字转换器运行过程中,第一级流水线已经重新启动累积下一个阶段的抖动,减少了空闲时间,提高了真随机数的质量和效率。在Xilinx Atrix-7平台进行了验证,该结构的硬件资源仅消耗了25个LUTs和13个DFFs,获得高达32.55 Mb/s的吞吐量。

In modern encryption systems,the demand for key randomness is constantly increasing.Therefore,the use of clock jitter,thermal noise and uncertain physical processes as entropy sources in a true random number generator has received widespread attention due to its ability to provide high-quality randomness.A configurable,lightweight,and efficient true random number generator is proposed.In this generator composed of a two-stage clock jitter pipelining with differential architecture,a design method based on stochastic mathematical models is applied.In the first stage of the pipelining,two ring oscillators accumulate jitter within a specified time,while in the second stage of the pipelining,a time to digital converter is constructed to quantify the Gaussian jitter output from the first stage using the small period difference between two ring oscillators that are approximately the same.Random bits are output by means of digital module.This structure was verified on Xilinx Atrix-7 platform.25 LUTs and 13 DFFs are consumed by the hardware resources,achieving a throughput of up to 32.55 Mb/s.