用于Pipelined-SAR模数转换芯片中的高精度比较器设计

Design of high precision comparator for Pipelined⁃SAR analog to digital converter chip

设计了一款可用于18 bit、2 Ms/s的流水线型逐次逼近型模数转换器(Pipelined-SAR ADC)的高精度比较器,该比较器的结构为三级预放大器+锁存器(latch),同时采用了一种失调电压消除技术,有效减小了比较器的失调电压。在TSMC 0.18μm的工艺下,使用Spectre对比较器进行仿真,结果表明,该比较器在1.8 mW的功耗下,输入失调电压标准差为131μV,噪声电压为15μV,满足高精度和低功耗的要求。

A high precision comparator of Pipelined Successive Approximation Analog⁃to⁃Digital Co⁃nverter(Pipelined-SAR ADC),which can be used for 18 bit accuracy and 2 Ms/s sampling rate,is designed.The comparator adopts the structure of three⁃level preamplifier+latch.At the same time,an offset voltage elimination technique was used to reduce the offset voltage of the comparator effectively.The comparator is implemented in TSMC 0.18μm CMOS technology and simulated in Spectre.The results show that the comparator achieves the standard deviation of input offset voltage of 131μV and RMS noise of 15μV at the power consumption of 1.8 mW,meeting the requirements of high accuracy and low power consumption.